The present invention relates generally to an output buffer for sending data signals, and more particularly to an output buffer suitable for use in high-speed data transfer.
In recent years the operation speeds of central processing units (CPUs), and the like, have continued to increase. As a result, in computer systems and the like, the speed at which data must be transferred between semiconductor devices, or printed circuit boards containing such devices, has also increased. To meet such higher data transfer speeds, high speed transmission line structures are typically employed. For example, a motherboard can include micro-striplines for transmitting data signals, or coaxial cables are included for connecting circuits on a printed circuit boards, or for connecting to printed circuit boards.
In the case of low frequency signals having relatively low data transmission rates, a signal wavelength can be much longer than a transmission line length. Thus, a signal phase can be nearly identical on all portions of the transmission line at a given time. As a result, even if noise is generated by signal reflection arising from impedance mismatch, because such noise is in phase with the signal, the signal waveform is not substantially deteriorated.
However, in the case of a high frequency signal, a signal waveform may become much shorter than the length of a transmission line. Thus, a signal phase varies according to the particular portion of the transmission line. As a result, the phase at which reflected noise affects the transmitted signal may not be known, and it can be possible for the reflected noise to significantly deteriorate signal quality.
One general way to address the above drawbacks for high frequency signals can be termination processing. Termination processing can include providing an impedance at a signal matching end or signal transmission end that matches a characteristic impedance of the transmission line. This can suppress noise generated by reflected signals.
FIG. 6 is a circuit diagram showing one example of a parallel termination arrangement made on a signal reception end. FIG. 7 is a circuit diagram showing one example of a series (or serial) termination made on a signal transmission end.
Referring now to FIG. 6, in a parallel termination arrangement a signal receiving end can be connected to a power supply voltage or ground potential through a resistor (terminal or terminating resistor). A terminal resistor can have an impedance equal to a characteristic impedance of the transmission line. In contrast, in the series termination arrangement of FIG. 7, a number of driver circuits (i.e., n driver stages, where n is a positive integer) can be arranged at a signal transmission end and operated in parallel. Each driver stage includes a p-channel metal-oxide-semiconductor field effect transistor (MOSFET) and an n-channel MOSFET. A resulting output impedance of such driver stages can made to equal a characteristic impedance of a transmission line.
The above parallel termination arrangement for a signal reception end is adapted for use with a high speed bus, as signal reflection can be reduced or eliminated. However, in such an arrangement a reception end can be connected to a power supply voltage (or ground potential) through a terminal resistor. Thus, a signal voltage is divided with an output impedance of a signal transmission side and the terminal resistor. As a result, a signal amplitude is decreased in order to increase noise margin. In addition, in the above parallel termination arrangement, a current will flow between a power supply voltage and ground potential through a terminal resistor, which may have a relatively low resistance. This can result in increased power consumption. Still further, adding a terminal resistor to various inputs can increase a resulting cost of a device.
In the case of a series termination made on a signal transmission side, because an output impedance can be made to match a characteristic impedance of a transmission line, there is no need to provide a terminal resistor. Thus, a signal transmission side can provide reduction in noise while at the same time preventing power consumption resulting from a terminal resistor. However, signal transmission side termination can have drawbacks, as signals reflected on a reception side are terminated on the transmission side. Consequently, if a series termination is applied to a bus arrangement, it can take more time to transfer a signal, as one portion of a bus can be closer to a signal transmission end. That is, a signal will have to make a round trip through an entire bus-type transmission line between the transmission of the signal and reception of the corresponding reflected signal.
In one-to-one communication, signal transmission sides can have a one-to-one correspondence with a signal reception. Thus, in such arrangements it is preferable to provide series termination on a signal transmission side, as this can reduce power consumption and reduce noise margin, as noted above.
To better understand the invention, an example of a conventional series termination arrangement, configured for one-to-one communication, will now be described.
Referring now to FIG. 8, an eye diagram is set forth showing a data transfer waveform for a conventional series termination arrangement.
In recent years, high speed data transfer interfaces have utilized a data reception circuit that includes an input buffer circuit with a differential amplifier circuit that meets the series stub terminated logic (SSTL) standard. In such an input buffer circuit, the level of a received signal is judged with respect to a reference voltage Vref (normally, Vref=Vdd/2). Received data can be pulse shaped, and the input buffer circuit can provide an output signal according to such a comparison with a reference voltage Vref level.
However, a reference voltage Vref provided to an input buffer circuit may vary (from Vref+ to Vrefxe2x88x92) due to uncontrollable conditions, such as ambient temperature, for example. Thus, to improve the stability of data reception, it is preferable that in a response like that of FIG. 8, an opening in the eye diagram be made as large as possible.
A first conventional series termination arrangement is shown by waveform 800. Waveform 800 shows how a series termination arrangement can provide a low noise response, hence the width of the signal can be relatively narrow. However, such an arrangement can have drawbacks. When an output impedance of an output buffer is made to match the characteristic impedance of a transmission line, a driving ability of such a circuit can be restricted. This results in the rise/fall time (referred to herein as the AC performance) of a driven pulse signal being lengthened. Consequently, if a desired data transfer rate is relatively high, it can be impossible to provide a response with a sufficiently large opening when represented by an eye diagram.
An output impedance of an output buffer can be reduced to thereby increase driving ability. This can shorten rise/fall times with respect to an impedance matched output buffer circuit. However, because a signal transmission end is no longer terminated with a matching impedance, reflected noise is generated, increasing a jitter component of a response. Such a second conventional arrangement is shown by waveform 802. As shown, additional noise an result in a waveform 802 of increased width when represented by an eye diagram.
In light of the above, it would desirable to provide an output buffer circuit that can have enhanced AC performance and noise suppression with respect to conventional approaches. Such an arrangement can result in a response that presents an enlarged opening when represented by an eye diagram.
The present invention may include an output buffer circuit for sending output data signals on a transmission line according to input data signals supplied from an internal circuit. The output buffer circuit can include a plurality of driver circuits connected in parallel for sending output data signals on the transmission line. Each driver circuit can have a predetermined output impedance. The output buffer circuit can also include a signal judging circuit that can drive a first predetermined number of the driver circuits according to an input data signal when the input data signal is continuously at one value for a predetermined time period. Such a first predetermined number of driver circuits can have an output impedance that essentially matches a characteristic impedance of the transmission line. The signal judging circuit may also drive a second predetermined number of the driver circuits according to an input data signal, when the input data signal transitions. Such a second predetermined number of driver circuits can have an output impedance that is lower than the characteristic impedance of the transmission line.
According to one aspect of the embodiments, a signal judging circuit can include an input sampling circuit for generating at least two judging values corresponding to a state of the input data signal during at least two time periods. The two judging values can have a first combination of values when the input data signal is continuously at one value for a predetermined time period. The two judging values can have second combination of values when the input data signal transitions.
According to another aspect of the embodiments, an input sampling circuit can include a first register circuit for storing an input signal level in response to a clock signal, and a second register circuit for storing an output value from the first register circuit in response to the clock signal.
According to another aspect of the embodiments, an input sampling circuit can include a first flip-flop circuit for storing an input signal level in response to a system clock signal, and a second flip-flop circuit for storing an output value from the first flip-flop in response to the system clock signal.
According to another aspect of the embodiments, a first combination of judging values can include all judging values having the same logic level, and can represent an input signal value that maintains a constant level for a predetermined amount of time. A second combination of judging values can include the judging values having different logic levels that can represent an input signal that makes a transition.
According to another aspect of the embodiments, a judging circuit can include judging values having at least a first judging value representing a later sample of an input signal than a second judging value. A signal judging circuit can also include a control circuit for driving the first driver circuit in response to the first judging value.
According to another aspect of the embodiments, a signal judging circuit can include judging values having at least a first judging value representing a later sample of an input signal than a second judging value. A signal judging circuit can also include a control circuit that activates a second driver circuit in response to a first judging value when the first signal value and second judging value have a predetermined combination.
According to another aspect of the embodiments, an output buffer circuit and internal circuit according to the above embodiments can be portions of the same integrated circuit.
The present invention may include another output buffer circuit for sending output data signals on a transmission line according to input data signals supplied from an internal circuit. The output buffer circuit can include a first driver circuit for sending data signals on a transmission line through an output impedance essentially equal to a characteristic impedance of the transmission line and a second driver circuit connected in parallel with the first driver circuit. When the second driver circuit is activated with the first driver circuit, an output impedance of the output buffer circuit can be lower than the characteristic impedance of the transmission line. The output buffer circuit may also include a signal judging circuit for driving the first driver circuit and not the second driver circuit according to an input signal when the input data signal is continuously at one level, and driving the first driver circuit and second driver circuit according to an input signal when the input data signal makes a transition.
According to one aspect of the embodiments, a signal judging circuit can include a first flip-flop and a second flip-flop connected in series for latching an input signal according to the timing of a clock signal. In addition, a control circuit can drive a first driver circuit according to an output of the first flip-flop, can drive a second driver circuit according to the output of the first flip-flop when the output of the first flip-flop is different than an output of the second flip-flop, and can stop the operation of the second flip-flop when the output of the first flip-flop is the same as the output of the second flip-flop.
According to another aspect of the embodiments, a control circuit can include a driver circuit for supplying a drive signal to the first driver circuit in accordance with the output of a first flip-flop. A control circuit can also include a first logic circuit for outputting a logical combination of the output of the first flip-flop and a second flip-flop, and a second logic circuit for outputting a logical combination of the output of the first flip-flop and the second flip-flop. In addition, a third logic circuit can output a logical combination of the output of the first flip-flop and an output of the first logic circuit to the second driver circuit, and a fourth logic circuit can output a logical combination of the output of the first flip-flop and an output of the second logic circuit to the second driver circuit.
According to another aspect of the embodiments, in the above arrangement, a driver circuit can include an inverter, a first logic circuit can include a logical OR-type gate, and a second logic circuit can include a logical AND-type gate. In addition, a third logic circuit can include a logical NAND-type gate and provide an output value to a first conductivity type output transistor within the second driver circuit, and a fourth logic circuit can include a logical NOR-type gate, and can provide an output value to a second conductivity type output transistor within the second driver circuit.
According to another aspect of the embodiments, a control circuit can include a driver circuit for supplying a drive signal to the first driver circuit in accordance with the output of a first flip-flop, a first logic circuit for outputting a logical combination of the output of the first flip-flop and a second flip-flop, and a second logic circuit for outputting a logical combination of the output of the first flip-flop and the second flip-flop. A control circuit may also include a first transfer gate and second transfer gate for supplying a first drive signal to the second driver circuit, and a third transfer gate and fourth transfer gate for supplying a second drive signal to the second driver circuit.
According to another aspect of the embodiments, in the above arrangement, a driver circuit can include an inverter, a first logic circuit can include a logical NAND-type gate and a second logic circuit can include a logical NAND-type gate. In addition, a first transfer gate and second transfer gate can be enabled in response to an output of the first logic circuit, and a third transfer gate and fourth transfer gate can be enabled in response to an output of the second logic circuit.
According to another aspect of the embodiments, first drive signal and second drive signal can be generated from the output of a driver circuit.
The present invention may also include an output buffer circuit having at least one first driver circuit coupled to a transmission line that includes an output impedance that essentially matches a characteristic impedance of the transmission line, and at least one second driver circuit coupled in parallel with the at least one first driver circuit. The output buffer circuit may also have a signal judging circuit that includes a control circuit that activates the second driver circuit in response to a transition in a received input signal, and deactivates the second driver circuit in response to the received input signal maintaining a same value for a predetermined period of time.
According to one aspect of the embodiments, the at least one second driver circuit can include a first conductivity type driver transistor and a second conductivity type driver transistor. In addition, a control circuit can include a first logic gate having one input coupled to a first detect signal, a second input coupled to a logical combination of the first detect signal and a second detect signal, and an output coupled to the first conductivity type driver transistor. The control circuit may further include a second logic gate having one input coupled to the first detect signal, a second input coupled to a different logical combination of the first detect signal and the second detect signal, and an output coupled to the second conductivity type driver transistor.
According to another aspect of the embodiments, the at least one second driver circuit can include a first conductivity type driver transistor and a second conductivity type driver transistor. In addition, a control circuit can include a first transfer gate that is enabled in response to a first logical combination of a first detect signal and a second detect signal that includes an input coupled the first detect signal and an output coupled to the first conductivity type driver transistor. A second transfer gate can be enabled in response to a second logical combination of the first detect signal and the second detect signal, and can include an input coupled to the first detect signal and an output coupled to the second conductivity type driver transistor.
According to another aspect of the embodiments, a signal judging circuit can further include a first judging circuit coupled to a signal input that outputs a first detect signal corresponding to a detected level of the received input signal, and a second judging circuit stores the detected level from the first judging circuit, and that outputs a second detect signal.
According to another aspect of the embodiments, a first judging circuit can store a detected level of a received input signal in response to a periodic signal, and a second judging circuit can store the detected level in response to a periodic signal.